CEB NT-97/06
31 October 97

Scintillator Monitor CARD (SMC)

for the TOF system

of the AMS experiment

I.D'Antone, G.Torromeo

Istituto Nazionale di fisica Nucleare

Bologna, Italy



The SMC control board (Scintillator Monitor Card) used in the Time of Flight (TOF) system for the AMS experimental apparatus is described.

The CPU in the crate is able, by means of the SMC, to set the Vref for the High Voltages system and the Vref for the readout card; furthermore it is able to read out the temperature sensors in the readout electronics.

The protocol used by the CPU to communicate with the SMC is also discussed. Finally some general considerations about the board reliability are reported.



Sezione di Bologna

1. Introduction

The AMS is an experiment designed to measure the amount of antimatter nuclei present in cosmic rays. Antimatter is identified by means of the absolute charge of a particle crossing the spectrometer and the sign of the charge determined by the curvature of the trajectory and from the flight direction as given by the TOF and Cerenkov counters [1].

The High Voltage Distribution Card (HVDC) designed for the Time Of Flight (TOF) detector has the purpose of providing individually programmable supply voltages to the 21 PMTs covering ¼ of a TOF detector plane.

The HVDC is split into two interconnected parts but it works as a single unit under the supervision of the AMS Slow Control System via a Scintillator Monitor Card (SMC).

By means of the SMC, the CPU is able to control the HDVC, i.e. the value of the primary High Voltage in the range 800 to 1100V. Furthermore the SMC gives the pattern of activation as well as the amplitude to a programmable LED pulser section in the HVDC, to inject test light pulses in the plastic scintillators.

The typical crate of the TOF system is composed of 6 SFEX (SFEX = SFET, SFEA, SFEC) cards performing the time to digital conversion, 1 SMC and a CPU (JDQS in fig.1).

2. SMC block diagram description

The SMC is the only module in the crate controlled by the JDQS (fig.1). To perform a read/write operation in the SMC or in the SFEX (SFEX = SFET, SFEA, SFEC) cards the JDQS must address the SMC.

In this way, by means of the SMC, the JDQS is able to set the 64 Vref for the TOF HV, ANTI HV, CEREN HV and the 16 Vref in each SFET; furthermore it can read out the two temperature sensors in each SFET.

In other words the SMC during a write cycle performs a buffer operation, while in a read cycle performs a switch of the 8bit data bus to connect the SFEX cards with the CPU JDQS.

A block scheme of the SMC is shown in the fig.2. The SMC card is divided in two parts: one half the SMC handles the SFEX cards in the top of the crate, while the other half handles the SFEX in the bottom of the crate.

A pASIC 7C384 (pASIC1) in one half the board is used to communicate with three SFEX cards. FPGA devices of the pASIC family (Cypress-QuickLogic) use the anti-fuse technology and have become popular with space flight designers. The same pASIC1 besides writes 4 DAC8800 to generate 32 analog signals for the VREF of the HV power supply. A DAC8800 contains 8 canals with serial data transmission. The DAC outputs are dispatched to 32 buffers LM6462 to give Vref voltages in the range 0V --> +5V or -5V --> 0V.

Another pASIC (pASIC2) handles the bottom half the crate and gives other 32 Vref voltages.

The best number of Vrefs generated by the SMC, for the HV system, has been evaluated in 64. Since the TOF PMs are 336 and the SMC cards are 8 (that is one for each crate), each SMC must generate 336/ 8= 42 signals for the VREF of the HV power supply. Additionally it must generate 2 levels for the main HV voltages + 2 levels for the led pulses. It must generate also other signals for the ANTI HV and CEREN HV systems [1]. Since each DAC contains eight channels per chip, to optimize the DAC + buffers utilization we have decided to generate 64 analog signals per SMC.



typical crate


3. The Communication Protocol

The SMC is the only module seen by the JDQS. As said above, the JDQS is able, by means of the SMC, to set the Vref for the HV system or the Vref for the SFET board and to read out the temperature sensors in the SFET board.

During a write cycle the JDQS, in a first phase, sends the address to identify the six SFEX boards or the SMC. In a second phase the JDQS sends the data that arrive to the board identified in the previous phase.



SMC block scheme

During a read cycle the JDQS, in a first phase, write the address of the SFEX to read (the SMC cannot be read). With this address the SMC identifies the bus "up" or "down" to connect to the JDQS bus. In a second phase the JDQS reads the data from this bus.

The address bits are decoded to select the parameters as described in fig.3

The TTL signal involved in the read/write cycles are the following:

D/A (data/address) 8 bits bidirectional signals

DAS (data/address select) 1 bit JDQS à SMC

WRS (write/read select) 1 bit JDQS à SMC

STB (strobe) 1 bit JDQS à SMC

In fig.4 the read and the write timing are shown .

4. The SMC layout.

In fig.5 is shown a photo of the board. We see the SMC divided in two parts having the same layout. The components employed are assembled in SMT (Surface Mount Technology) packages. The front panel contains 4 connectors. In two 37 pins connectors, the SMC gives 42+2+2 analog signals, +12 V and -5 V protected (current limited) power supplies to the TOF PM system.



The addressing scheme




Read/Write timing

Moreover, in two 25 pins connectors, the SMC gives 18 other signals to ANTI HV and CEREN HV and four +12 V protected (current limited) power supplies.

To prevent the possible LATCH-UP of the pASIC, a suitable circuit (transistors near the pASICs in the photo) on the power supply of each FPGA has been designed.

The board is realized following the mechanical dimension of the EUROCARD standard 6U.


SMC layout


5. General considerations about the SMC reliability.

To increase the reliability of the board we have considered several techniques: component selection, derating, burn-in, redundancy.

For space application, because of good density and low cost, Field Programmable Gate Arrays (FPGAs) are attractive. FPGA devices use the anti-fuse technology (Cypress-QuickLogic, Actel) and have become popular with space flight designers. We have used Cypress-Quicklogic FPGAs. They are programmed by "burning" one or more anti-fuses, which otherwise have a very high electrical resistance and separate electrical nodes. During programming a low resistance path between nodes is provided.

From the reliability report of the Cypress company [2] the overall reliability of the pASIC380, which we have used in the SMC board, is 19 FITs with a 60% confidence level.

The Failure In Time (FIT) is a measure of the failure rate in 109 device hours, e.g. 1 FIT= 1 failure in 109 device hours [3].

For the other components in the SMC board we have selected devices delivered by Company having a documented Reliability Program and devices having an ultra-low power consumption.

We have used DACs from Analog Devices and micro-power Operational Amplifiers from National Semiconductor. All components employed are SMT (Surface Mount Technology) devices that offer a significant advantage in terms of reduced size and weight.

Furthermore we have considered the architecture of the SMC; it has been designed in two equal independent parts to have a higher reliability for half crate electronics and for the HV Vref generation.


In this report we have described the control board (SMC) used in the TOF system for the AMS experimental apparatus. The block diagram and the CPU communication protocol have been reported.

Finally some general considerations about the SMC reliability have been discussed.


[1] AMS collaboration, "Ricerca di antimateria nell'universo", Programma scientifico INFN,

Gruppo II, 1996.

[2] Cypress, "Programmable Logic DATA BOOK", 1996.

[3] I.D'Antone, "Reliability and redundancy in complex digital system: an overview", internal note,

CEB NT-96/03, 1996.

Page edited by Bisi Fabio